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d a t a sh eet product speci?cation file under integrated circuits, ic01 2001 mar 05 integrated circuits saa7706h car radio digital signal processor (dsp)
2001 mar 05 2 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h contents 1 features 1.1 hardware 1.2 software 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagram 7 pinning 8 functional description 8.1 analog front-end 8.1.1 the realization of common mode input with aic 8.1.2 realization of the auxiliary input with volume control 8.1.3 realization of the fm input control 8.1.4 pins vdacn1, vdacn2 and vdacp 8.1.5 pin vrefad 8.1.6 supply of the analog inputs 8.2 the signal audio path for input signals cd, tape, aux, phone, nav and am 8.3 signal path for level information 8.4 signal path from fm_mpx input to iac and stereo decoder 8.4.1 noise level 8.4.2 mono or stereo switching 8.4.3 the automatic lock system 8.5 dcs clock 8.6 the interference absorption circuit (iac) 8.6.1 general description 8.7 the filter stream dac (fsdac) 8.7.1 interpolation filter 8.7.2 noise shaper 8.7.3 function of pin pom 8.7.4 power-off plop suppression 8.7.5 pin vrefda for internal reference 8.7.6 supply of the filter stream dac 8.8 clock circuit and oscillator 8.8.1 supply of the crystal oscillator 8.9 the phase-locked loop circuit to generate the dsps and other clocks 8.10 supply of the digital part (v ddd3v1 to v ddd3v4 ) 8.11 cl_gen, audio clock recovery block 8.12 external control pins 8.12.1 dsp1 8.12.2 dsp2 8.13 i 2 c-bus control (pins scl and sda) 8.14 digital serial inputs/outputs and spdif inputs 8.14.1 general description digital serial audio inputs/outputs 8.14.2 general description spdif inputs (spdif1 and spdif2) 8.14.3 digital data stream formats 8.15 rds demodulator (pins rds_clock and rds_data) 8.15.1 clock and data recovery 8.15.2 timing of clock and data signals 8.15.3 buffering of rds data 8.15.4 buffer interface 8.16 dsp reset 8.17 test mode connections (pins tscan, rtcb and shtcb) 9i 2 c-bus format 9.1 addressing 9.2 slave address (pin a0) 9.3 write cycles 9.4 read cycles 9.5 saa7706h hardware registers 9.5.1 saa7706h dsps registers 9.6 i 2 c-bus memory map specification 10 limiting values 11 thermal characteristics 12 characteristics 13 rds and i 2 s-bus timing 14 i 2 c-bus timing 15 software description 16 application diagram 17 package outline 18 soldering 18.1 introduction to soldering surface mount packages 18.2 reflow soldering 18.3 wave soldering 18.4 manual soldering 18.5 suitability of surface mount ic packages for wave and reflow soldering methods 19 data sheet status 20 definitions 21 disclaimers 22 purchase of philips i 2 c components
2001 mar 05 3 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 1 features 1.1 hardware 5-bitstream 3rd-order sigma-delta analog-to-digital converters (adcs) with anti-aliasing broadband input filter 1-bitstream 1st-order sigma-delta adc with anti-aliasing broadband input filter 4-bitstream digital-to-analog converters (dacs) with 128-fold oversampling and noise shaping integrated semi-digital filter; no external post filter required for dac dual media support: allowing separate front-seat and rear-seat signal sources and separate control simultaneous radio and audio processing digital fm stereo decoder digital fm interference suppression rds demodulation via separate adc; with buffered output option two mono common-mode rejection ratio (cmrr) input stages for voice signals from phone and navigation inputs phone and navigation mixing at dac front outputs two stereo cmrr input stages (cd-walkman and cd-changer etc.) analog single-ended tape and aux input separate am-left and am-right inputs in the event of use of external am stereo decoder one digital input: i 2 s-bus or lsb-justified format two digital inputs: spdif format co-dsp support via i 2 s-bus or lsb-justified format audio output short-circuit protected i 2 c-bus controlled (including fast mode) most bus interfacing (details in separate manual) phase-locked loop derives the internal clocks from one common fundamental crystal oscillator combined am/fm level input pin compatible with saa7705 and saa7708 all digital inputs are tolerant of 5 v input levels all analog inputs have high gsm immunity low number of external components required - 40 to +85 c operating temperature range easy applicable. 1.2 software improved fm weak signal processing integrated 19 khz mpx filter; de-emphasis and stereo detection electronic adjustments: fm or am level, fm channel separation, dolby? (1) level baseband audio processing (treble, bass, balance, fader and volume) four channel 5-band parametric equalizer 9-bands mono audio spectrum analyzer extended beep functions with tone sequencer for phone rings large volume jumps e-power interpolated to prevent zipper noise dual media support; allowing separate front-seat and rear-seat signal sources and separate control dynamic loudness or bass boost audio level monitor tape equalization and music search system (mss) detection for tape dolby-b tape noise reduction (at 44.1 khz only) dynamics compression available in all modes cd de-emphasis processing voice-over possibility for phone and navigation signals improved am signal processing digital am cquam stereo decoder (not in all rom_codes available) digital am interference suppression soft audio mute rds update processing: pause detection, mute and signal-quality sensor-freeze general purpose tone generator (1) dolby available only to licensees of dolby laboratories licensing corporation, san francisco, ca94111, usa, from whom licensing and application information must be obtained. dolby is a registered trade-mark of dolby laboratories licensing corporation.
2001 mar 05 4 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h noise generator allows for frequency response measurements boot-up rom for fast start-up signal level, noise and multipath detection for am or fm signal quality information am co-channel and adjacent channel detection (not in all rom_codes available). 2 applications high-end car radio systems. 3 general description the saa7706h performs all the signal functions in front of the power amplifiers and behind the car radio tuner am and fm outputs and the cd, tape and phone inputs. these functions are: interference absorption stereo decoding for fm and am (stereo) rds-demodulation fm and am weak signal processing (soft mute, sliding stereo and high cut) dolby-b tape noise reduction cd de-emphasis function audio controls for volume, balance, fader, tone and dynamics compression. some functions have been implemented in hardware (fm stereo decoder, rds-demodulator and fm interference absorption circuit (iac) and are not freely programmable. digital audio signals from external sources with the philips i 2 s-bus and the lsb-justified 16, 18, 20 and 24 bits format or spdif format are accepted. the big advantage of this saa7706h device is the dual media support; this enables independent front seat and rear seat audio sources and control. 4 quick reference data symbol parameter conditions min. typ. max. unit supplies v dd operating supply voltage all v dd pins with respect to v ss 3 3.3 3.6 v i ddd supply current of the digital part dsp1 at 50 mhz; dsp2 at 62.9 mhz - 110 150 ma i dda supply current of the analog part zero input and output signal - 40 60 ma p tot total power dissipation dsp1 at 50 mhz; dsp2 at 62.9 mhz - 540 750 mw fm_mpx input v i(con)(max)(rms) maximum conversion input level (rms value) thd < 1%; volfm = 00h 0.33 0.368 - v thd total harmonic distortion input signal 0.368 v (rms) at 1 khz; bandwidth = 19 khz; volfm = 00h -- 70 - 65 db - 0.03 0.056 % s/n signal-to-noise ratio input stereo input signal at 1 khz; bandwidth = 40 khz; 0 db reference = 0.368 v (rms); volfm = 00h 75 81 - db cd, tape, aux and am inputs v i(con)(max)(rms) maximum conversion input level (rms value) thd < 1% 0.6 0.66 - v
2001 mar 05 5 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 5 ordering information thd total harmonic distortion input signal 0.55 v (rms) at 1 khz; bandwidth = 20 khz -- 85 - 75 db s/n signal-to-noise ratio input signal at 1 khz; bandwidth = 20 khz; 0 db reference = 0.55 v (rms) 85 90 - db fsdac (thd + n)/s total harmonic distortion-plus-noise to signal ratio (measured with system one) at 0 db -- 90 - 85 db at - 60 db; a-weighted -- 37 - db s/n signal-to-noise ratio (measured with system one) code = 0; a-weighted - 105 - db crystal oscillator f xtal crystal frequency - 11.2896 - mhz type number package name description version saa7706h qfp80 plastic quad ?at package; 80 leads (lead length 1.95 mm); body 14 20 2.8 mm sot318-2 symbol parameter conditions min. typ. max. unit
2001 mar 05 6 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 6 block diagram o ok, full pagewidth mgt457 fm_rds 79 level- adc rds demodulator digital source selectors digital i/o digital source selector xtal oscillator spdif2 spdif1 mono adc3 stereo adc2 stereo adc1 i 2 s-bus spdif a i 2 c-bus analog source selector sel_fr 61 fm_mpx 80 tape_r 68 25 24 cd_data 28 tape_l 69 cd_r_gnd 14 stereo cmrr inputs vrefad 78 vdacn1 2 vdacp 1 cd_(l)_gnd 77 cd_r 70 cd_l 72 nav_gnd 4 mono cmrr inputs level 3 signal level dsp1 dsp2 quad fsdac 16 flv 13 frv 9 rlv 6 rrv 5 pom 10 v ssa2 11 v dda2 20 loopo b cd_ws 27 cd_clk 29 a0 56 dsp_reset 42 rtcb 43 shtcb 44 tscan 45 v dda1 74 vdacn2 76 v ssa1 75 v ddd3v5 46 v ddd3v6 36 v ddd3v7 22 v ssd3v1 49 v ssd3v2 50 v ssd3v3 53 v ssd3v4 54 v ssd3v5 47 v ssd3v6 37 v ssd3v7 23 v ddd3v1 48 v ddd3v2 51 v ddd3v3 52 v ddd3v4 55 dsp1_out2 41 dsp1_out1 40 dsp1_in2 39 dsp1_in1 38 dsp2_inout4 19 dsp2_inout3 18 dsp2_inout2 15 dsp2_inout1 17 sysfs 26 v ss(osc) 62 v dd(osc) 65 tp1 21 sda 58 osc_out 64 osc_in 63 rds_clock 59 rds_data 60 scl 57 signal quality phone volume phone_gnd 73 phone 71 aux_r 8 aux_l 7 am_r/am 66 am_l/nav 67 iac saa7706h stereo decoder + + 12 vrefda 34 iis_out1 35 iis_out2 30 iis_clk 33 iis_ws 31 iis_in1 32 iis_in2 fig.1 block diagram.
2001 mar 05 7 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 7 pinning symbol pin pin type description vdacp 1 apio positive reference voltage adc1, adc2, adc3 and level-adc vdacn1 2 apio ground reference voltage adc1 level 3 apio gsmcap level input pin; via this pin the level of the fm signal or level of the am signal is fed to the dsp1; the level information is used in the dsp1 for dynamic signal processing nav_gnd 4 apio gsmcap common mode reference input pin of the navigation signal (pin am_l/nav) pom 5 apio power-on mute of the qfsdac; timing is determined by an external capacitor rrv 6 apio rear; right audio output of the qfsdac aux_l 7 apio left channel of analog aux input aux_r 8 apio right channel of analog aux input rlv 9 apio rear; left audio output of the qfsdac v ssa2 10 vssco ground supply analog part of the qfsdac and spdif bitslicer v dda2 11 vddco positive supply analog part of the qfsdac and spdif bitslicer vrefda 12 apio voltage reference of the analog part of qfsdac frv 13 apio front; right audio output of the qfsdac cd_r_gnd 14 apio common-mode reference input pin for analog cd_r or tape_r in the event of separated ground reference pins for left and right are used dsp2_inout2 15 bpts5thdt5v ?ag input/output 2 of the dsp2-core (dsp2-?ag) i 2 c-bus con?gurable flv 16 apio front; left audio voltage output of the qfsdac dsp2_inout1 17 bpts5thdt5v ?ag input/output 1 of the dsp2-core (dsp2-?ag) i 2 c-bus con?gurable dsp2_inout3 18 bpts5thdt5v ?ag input/output 3 of the dsp2-core (dsp2-?ag) i 2 c-bus con?gurable dsp2_inout4 19 bpts5thdt5v ?ag input/output 4 of the dsp2-core (dsp2-?ag) i 2 c-bus con?gurable loopo 20 bpts5tht5v sysclk output (256f s ) tp1 21 ipthdt5v for test purpose only; this pin may be left open or connected to ground v ddd3v7 22 vdde positive supply (peripheral cells only) v ssd3v7 23 vsse ground supply (peripheral cells only) spdif2 24 apio spdif input 2; can be selected instead of spdif1 via i 2 c-bus bit spdif1 25 apio spdif input 1; can be selected instead of spdif2 via i 2 c-bus bit sysfs 26 ipthdt5v system f s clock input cd_ws 27 ipthdt5v digital cd-source word select input; i 2 s-bus or lsb-justi?ed format cd_data 28 bpts10thdt5v digital cd-source left-right data input; i 2 s-bus or lsb-justi?ed format cd_clk 29 ipthdt5v digital cd-source clock input i 2 s-bus or lsb-justi?ed format iis_clk 30 ots10ct5v clock output for external i 2 s-bus receiver; for example headphone or subwoofer iis_in1 31 ipthdt5v data 1 input for external i 2 s-bus transmitter; e.g. audio co-processor iis_in2 32 ipthdt5v data 2 input for external i 2 s-bus transmitter; e.g. audio co-processor iis_ws 33 ots10ct5v word select output for external i 2 s-bus receiver; for example headphone or subwoofer iis_out1 34 ots10ct5v data 1 output for external i 2 s-bus receiver or co-processor iis_out2 35 ots10ct5v data 2 output for external i 2 s-bus receiver or co-processor
2001 mar 05 8 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h v ddd3v6 36 vdde positive supply (peripheral cells only) v ssd3v6 37 vsse ground supply (peripheral cells only) dsp1_in1 38 bpts10thdt5v ?ag input 1 of the dsp1-core dsp1_in2 39 bpts10thdt5v ?ag input 2 of the dsp1-core dsp1_out1 40 op4mc ?ag output 1 of the dsp1-core dsp1_out2 41 op4mc ?ag output 2 of the dsp1-core dsp_reset 42 iptut5v general reset of chip (active low) rtcb 43 ipthdt5v asynchronous reset test control block; connect to ground (internal pull-down) shtcb 44 ipthdt5v shift clock test control block (internal pull-down) tscan 45 ipthdt5v scan control active high (internal pull-down) v ddd3v5 46 vdde positive supply (peripheral cells only) v ssd3v5 47 vsse ground supply (peripheral cells only) v ddd3v1 48 vddi positive supply (core only) v ssd3v1 49 vssis ground supply (core only) v ssd3v2 50 vssco ground supply (core only) v ddd3v2 51 vddco positive supply (core only) v ddd3v3 52 vddco positive supply (core only) v ssd3v3 53 vssco ground supply (core only) v ssd3v4 54 vssis ground supply (core only) v ddd3v4 55 vddi positive supply (core only) a0 56 ipthdt5v slave sub-address i 2 c-bus selection or serial data input test control block scl 57 iptht5v serial clock input i 2 c-bus sda 58 iic400kt5v serial data input/output i 2 c-bus rds_clock 59 bpts10tht5v radio data system bit clock output or rds external clock input i 2 c-bus bit controlled rds_data 60 ops10c radio data system data output sel_fr 61 iptht5v ad input selection switch to enable high ohmic fm_mpx input at fast tuner search on fm_rds input v ss(osc) 62 vssco ground supply (crystal oscillator only) osc_in 63 apio crystal oscillator input osc_out 64 apio crystal oscillator output v dd(osc) 65 vddco positive supply (crystal oscillator only) am_r/am 66 apio gsmcap right channel am audio frequency or am input in the event of mono; analog input pin am_l/nav 67 apio gsmcap left channel am audio frequency or input of common mode navigation signal; analog input pin tape_r 68 apio gsmcap right channel of analog tape input tape_l 69 apio gsmcap left channel of analog tape input cd_r 70 apio gsmcap right channel of analog cd input phone 71 apio gsmcap common mode phone signal, analog input pin cd_l 72 apio gsmcap left channel of analog cd input symbol pin pin type description
2001 mar 05 9 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h table 1 brief explanation of used pin types phone_gnd 73 apio gsmcap common mode reference input pin of the phone signal v dda1 74 vddco positive supply analog (adc1, adc2, adc3 and level-adc only) v ssa1 75 vssco ground supply analog (adc3 and level-adc only) vdacn2 76 apio ground reference voltage (adc2) cd_(l)_gnd 77 apio gsmcap common mode reference input pin for analog cd or tape or in the event of separated ground reference pins used for cd_l or tape_l vrefad 78 apio common mode reference voltage adc1, adc2, adc3 and level-adc fm_rds 79 apio gsmcap fm rds signal; analog input pin fm_mpx 80 apio gsmcap fm multiplex signal; analog input pin pin type explanation apio 3-state i/o analog; i/o pad cell; actually pin type vddco apio gsmcap 3-state i/o analog; i/o pad cell; actually pin type vddco with high gsm immunity bpts5thdt5v 43 mhz bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; ttl; hysteresis; pull-down; 5 v tolerant bpts10tht5v 21 mhz bidirectional pad; push-pull input; 3-state output; 10 ns slew rate control; ttl; hysteresis; 5 v tolerant bpts10thdt5v 21 mhz bidirectional pad; push-pull input; 3-state output; 10 ns slew rate control; ttl; hysteresis; pull-down; 5 v tolerant iic400kt5v i 2 c-bus pad; 400 khz i 2 c-bus speci?cation; ttl; 5 v tolerant iptht5v input pad buffer; ttl; hysteresis; 5 v tolerant ipthdt5v input pad buffer; ttl; hysteresis; pull-down; 5 v tolerant iptut5v input pad buffer; ttl; pull-up; 5 v tolerant op4mc output pad buffer; 4 ma output drive; cmos; slew rate control; 50 mhz ots10ct5v output pad buffer; 3-state, 10 ns slew rate control; cmos; 5 v tolerant ops10c output pad buffer; 4 ma output drive; cmos; slew rate control; 21 mhz vdde v dd supply peripheral only vsse v ss supply peripheral only vddco v dd supply to core only vssco v ss supply to core only (vssco does not connect the substrate) vddi v dd supply to core and peripheral vssis v ss supply to core and peripheral; with substrate connection symbol pin pin type description
2001 mar 05 10 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h handbook, full pagewidth saa7706h mgt458 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 64 63 62 61 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 rds_data rds_clock sda scl a0 osc_out osc_in v ss(osc) sel_fr v ddd3v4 v ssd3v4 v ssd3v3 v ddd3v3 v ddd3v2 v ssd3v2 v ssd3v1 v ddd3v1 v ssd3v5 v ddd3v5 tscan shtcb rtcb dsp_reset dsp1_out2 pom rrv aux_l aux_r rlv vdacp vdacn1 level nav_gnd v ssa2 v dda2 vrefda frv cd_r_gnd dsp2_inout2 flv dsp2_inout1 dsp2_inout3 dsp2_inout4 loopo tp1 v ddd3v7 v ssd3v7 spdif2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 spdif1 sysfs cd_ws cd_data cd_clk iis_clk iis_in1 iis_in2 iis_ws iis_out1 iis_out2 v ddd3v6 v ssd3v6 dsp1_in1 dsp1_in2 dsp1_out1 fm_mpx fm_rds vrefad cd_(l)_gnd vdacn2 v ssa1 v dda1 phone_gnd cd_l phone cd_r tape_l tape_r am_l/nav am_r/am v dd(osc) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 fig.2 pinning diagram.
2001 mar 05 11 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 8 functional description 8.1 analog front-end the analog front-end consists of two identical sigma-delta stereo adcs (adc1 and adc2) with several input control blocks for handling common mode signals and acting as input selector. a mono version (adc3) is added for handling rds signals. also a first-order sigma-delta adc for tuner level information is incorporated. the switches s1 and s2 select (see fig.3) between the fm_mpx/fm_rds and the cd, tape, aux, am, phone and nav connection to adc1 and adc2. the inputs cd, tape, aux, am, phone and nav can be selected with the audio input controls (aic1/2). the ground reference (g0 and g1) can be selected to be able to handle common mode signals for cd or tape. the ground reference g0 is connected to an external pin and g1 is internally referenced (see fig.4). the phone and nav inputs have their own cmrr input stage and can be redirected to adc1/2 via the audio input control (aic). for pin compatibility with saa7704, saa7705 and saa7708 the am is combined with the nav input. it is also possible to directly mix phone or nav (controlled with mixc) with the front fsdac channels after volume control. the fm inputs (fm_mpx/fm_rds) can be selected with external pin sel_fr. the fm and rds input sensitivity can be adjusted with volfm and volrds via i 2 c-bus.
2001 mar 05 12 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h mgt459 handbook, full pagewidth level-adc clklevel levelo rds mono (rds) adc3 1 0 stereo adc1 1 0 left1 right1 adf1_a adf3 fmhsnr_adc1 clkadc2 clkadc2 volrds(5:0) s1 1 0 s3 0 1 stereo adc2 1 0 left2 right2 fmhsnr_adc2 clkadc2 s2 charge_pump mixc 1 0 volfm(5:0) 0 1 volmix(4:0) mix volmix(5:2) located in firdac 0 1 gndrc1 aic1(2:0) 1 0 x00 x01 x10 011 111 x00 x01 x10 011 111 0 1 gndrc2 gndc2 aic2(2:0) 1 0 1 0 x00 x01 x10 011 111 gndc1 level sel_fr fm_rds fm_mpx cd_l tape_l aux_l cd_r tape_r am_r/am aux_r cd_(l)_gnd cd_r_gnd vrefad phone_gnd phone nav_gnd am_l/nav 1 0 3 61 79 80 72 69 7 70 68 66 8 77 78 14 71 73 67 4 x00 x01 x10 011 111 midref cmrr cmrr adf1_b mux mux mux mux mux mux mux mux mux mux mux mux mux mux mux mux mux fig.3 analog front-end switch diagram.
2001 mar 05 13 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 8.1.1 t he realization of common mode input with aic a high common mode rejection ratio can be created by the use of the ground return pin. pin cd_(l)_gnd can be used in the case that the left and right channel have one ground return line. cd_(l)_gnd and cd_r_gnd can be used for separated left and right ground return lines. the ground return lines can be connected via the switch gndc1/2 and gndrc1/2 (see fig.4) to the plus input of the second operational amplifier in the signal path. the signal of which a high common mode rejection ratio is required has a signal and a common signal as input. the common signal is connected to the cd_(l)_gnd and/or cd_r_gnd input. the actual input can be selected with audio input control aic1/2(1:0). in fig.4 the cd input is selected. in this situation both signal lines going to s1/2 in front of the adc will contain the common mode signal. the adc itself will suppress this common mode signal with a high rejection ratio. the inputs cd_l and cd_r in this example are connected via an external resistor tap of 82 k w and 100 k w to be able to handle larger input signals. the 100 k w resistors are needed to provide a dc biasing of the operational amplifiers oa1 and oa2. the 1 m w resistor provides dc biasing of oa3 and oa4. if no external resistor tap is needed the resistors of 100 k w and 1 m w still have to provide dc biasing. only the 82 k w resistor can be removed. the impedance level in combination with parasitic capacitance at input cd_l or cd_r determines for a great deal the achievable common rejection ratio. handbook, full pagewidth mgt460 72 cd_l 77 cd_(l)_gnd oa2 oa4 78 vrefad 14 to mux s1/2 aic1/2(1:0) gndc1/2 gndrc1/2 00 01 10 g1 g0 11 cd_r_gnd 70 cd_r on-chip off-chip right left ground right from cd-player analog ground left 10 k w 82 k w 82 k w 1 m w 1 m w 100 k w 100 k w 10 k w 10 k w midref oa1 oa3 to mux s1/2 10 k w 10 k w 10 k w 00 01 10 11 mux mux fig.4 example of the use of common mode analog input in combination with input resistor tap.
2001 mar 05 14 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h handbook, full pagewidth mgt461 adc 0 db (full-scale) 660 mv (rms) gain audio audio digital filter 5 db gain dsp2 stereo decoder 3 db gain dsp1 - 2 db (full-scale) fig.5 audio gain through adc and digital filter path to dsp. 8.1.2 r ealization of the auxiliary input with volume control a differential input with volume control for mixing to the front left or front right of both dac outputs is provided. the inputs consist of a phone and nav input. both are accompanied with their ground return lines. after selection of phone or nav the volume can be changed from about +18 to - 22.5 db in 27 steps and mute (mix output). this signal can be added to the left and/or right front dac channels. the output signals of both input circuits can also be switched to adc1 and/or adc2, depending on the settings of audio input control 1 (aic1) and audio input control 2 (aic2), without volume control (see fig.3). 8.1.3 r ealization of the fm input control the gain of the circuit has a maximum of 2.26 (7.08 db). this results in an input level of 368 mv for full-scale, which means 0 db (full-scale) at the dsp1 input via the stereo decoder (see fig.6). the gain can be reduced in steps of 1.5 db. when the gain is set to - 3.4 db the input level becomes 1229 mv for full-scale. this setting accounts for the 200 mv (rms) input sensitivity at 22.5 khz sweep and a saturation of the input at 138 khz sweep. rds update: for rds update the fast access pin sel_fr must be made high. in that case the fm_rds signal also goes through the path that was set for fm_mpx. in this situation the signal must be obtained via the fm_rds input and a noise sample can be retrieved. the input fm_mpx gets high-ohmic. charging of the coupling capacitor connected to pin fm_mpx is no longer possible. handbook, full pagewidth mgt462 adc 0 db (full-scale) 831 mv (rms) gain fm audio digital filter 5 db gain dsp2 stereo decoder 3 db gain dsp1 fig.6 fm gain path through stereo decoder to dsp1.
2001 mar 05 15 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 8.1.4 p ins vdacn1, vdacn2 and vdacp these pins are used as negative and positive reference for the adc1, 2, 3 and the level-adc. they have to be directly connected to the v ssa1 and filtered v dda1 for optimal performance (see figs 25 and 26). 8.1.5 p in vrefad via this pin the midref voltage of the adcs is filtered. this midref voltage is used as half supply voltage reference of the adcs. external capacitors (connected to v ssa1 ) prevent crosstalk between switch cap dacs of the adcs and buffers and improves the power supply rejection ratio of all components. this pin is also used in the application as reference for the inputs tape and cd (see fig.4). the voltage on pin vrefad is determent by the voltage on pins vdacp and vdacn1 or vdacn2 and is found as: 8.1.6 s upply of the analog inputs the analog input circuit has separate power supply connections to allow maximum filtering. these pins are v ssa1 for the analog ground and v dda1 for the analog power supply. 8.2 the signal audio path for input signals cd, tape, aux, phone, nav and am the left and right channels are converted and down-sampled by the adf1_a, adf1_b. this data stream is converted into a serial format and fed to the dsp1 and dsp2 source selectors. in figs 7 and 8 the overall and detailed frequency response curves of the analog-to-digital audio decimation path based on a 44.1 khz sample frequency are shown. v vrefad v vdacp v vdacn1,2 C 2 --------------------------------------------------- - = handbook, full pagewidth 0 - 250 0 100 mgt463 300 500 400 200 - 200 - 150 - 100 - 50 f (khz) a (db) fig.7 overall frequency response curve analog-to-digital audio path decimation based on a 44.1 khz sample frequency.
2001 mar 05 16 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h handbook, full pagewidth 20 - 140 010 mgt464 30 50 40 20 - 120 - 100 - 80 - 20 0 - 60 - 40 f (khz) a (db) fig.8 detailed frequency response curve analog-to-digital audio path decimation based on a 44.1 khz sample frequency.
2001 mar 05 17 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 8.3 signal path for level information for fm weak signal processing, for am and fm purposes (absolute level and multipath) a level input is implemented (pin level). in the event of radio reception the clocking of the filters and the level-adc is based on a 38 khz sampling frequency. a dc input signal is converted by a bitstream sigma-delta adc followed by a decimation filter. the input signal has to be obtained from a radio part. the tuner must deliver the level information of either am or fm to pin level. the input signal for level must be in the range 0 to 3.3 v (v vdacp - v vdacn ). the 9-bit level-adc converts this input voltage in steps with a resolution better than at least 14 mv over the 3.3 v range. the tolerance on the gain is less than 2%. the msb is always logic 0 to represent a positive level. input level span can be increased by an external resistor tap. the high input impedance of the level-adc makes this possible. the decimation filter reduces in the event of an 38 khz based clocking regime the bandwidth of the incoming signal to a frequency range of 0 to 29 khz with a resulting f s = 76 khz. the response curve is given in fig.9. the level information is sub-sampled by the dsp1 to obtain a field strength and a multipath indication. these values are stored in the coefficient or data ram. via the i 2 c-bus they can be read and used in other microcontroller programs. handbook, full pagewidth 10 010 40 30 80 70 60 50 20 - 40 - 50 - 60 - 10 0 - 30 - 20 f (khz) a (db) mgt465 fig.9 frequency response level-adc and decimal filter.
2001 mar 05 18 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 8.4 signal path from fm_mpx input to iac and stereo decoder the fm_mpx signal is after selection available at one of three adcs (adc1, 2 and 3). the multiplex fm signal is converted to the digital domain in adc1, 2 and 3 through a bitstream adc. improved performance for fm stereo can be achieved by means of adapting the noise shaper curve of the adc to a higher bandwidth. the first decimation takes place in two down-sample filters. these decimation filters are switched by means of the i 2 c-bus bit wide_narrow in the wide or narrow band position. in the event of fm reception it must be in the narrow position. after selection of one of the adcs, the fm_mpx path it is followed by the iac and the fm stereo decoder. one of the two mpx filter outputs contains the multiplex signal with a frequency range of 0 to 60 khz. the overall low-pass frequency response of the decimation filters is shown in fig.10. handbook, full pagewidth - 140 0 100 mgt466 300 500 400 200 - 120 - 100 - 80 - 20 0 - 60 - 40 f (khz) a (db) fig.10 overall frequency response of adc1, adc2 and decimation filters.
2001 mar 05 19 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h the outputs of the stereo decoder to the dsp1, which are all running on a sample frequency of 38 khz are: pilot presence indication: pilot-i. this 1-bit signal is low for a pilot frequency deviation <4 khz and high for a pilot frequency deviation >4 khz and locked on a pilot tone. left and right fm reception stereo signal: this is the 18-bit output of the stereo decoder after the matrix decoding. noise level (see also section 8.4.1): which is retrieved from the high-pass output of the mpx filter. the noise level is detected and filtered in the dsp1 and is used to optimize the fm weak signal processing. normally the fm_mpx input and the fm_rds input have the same source. if the fm input contains a stereo radio channel, the pilot information is switched to the digitally controlled sampling (dcs) clock generation and the dcs clock is locked to the 256 38 khz of the pilot. in this case this locked frequency is also used for the rds path ensuring the best possible performance. except from the above mentioned theoretical response also the non-flat frequency response of the adc has to be compensated in the dsp1 program. handbook, full pagewidth 010 mgt467 30 70 60 50 40 20 - 100 - 80 - 20 0 - 60 - 40 f (khz) a (db) fig.11 transfer of mpx signal at the output of the stereo decoder.
2001 mar 05 20 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 8.4.1 n oise level the high-pass 1 (hp1 or narrow band noise level filter) output of the second mpx decimation filter in a band from 60 khz to 120 khz is detected with an envelope detector and decimated to a frequency of 38 khz. the response time of the detector is 100 m s. another option is the high-pass 2 (hp2 or wide band noise level filter). this output of the first mpx decimation filter is in a band from 60 to 240 khz. it has the same properties and is also decimated to the same 38 khz. which of the signals is used (hp1 or hp2) is determined by the i 2 c-bus bit sel_nsdec. the resulting noise information is rectified and has a word length of 10 bits. this means that the lowest and/or the highest possible level is not used. the noise level can be detected and filtered in the dsp1-core and be used to optimize the fm weak signal processing. the transfer curves of both filters before decimation are shown in fig.12. handbook, full pagewidth - 140 0 100 50 mgt468 200 300 250 150 - 120 - 100 - 80 - 20 0 (1) (2) - 60 - 40 f (khz) a (db) fig.12 frequency response of noise level before decimation. (1) noise with wide band digital filter. (2) noise with small band digital filter. 8.4.2 m ono or stereo switching the dcs block uses a sample rate converter to derive from the xtal clock, via a pll, a 512 multiple of 19 khz (9.728 mhz). in the event of mono reception the dcs circuit generates a preset frequency of n 19 khz 2 hz. in the event of stereo reception the frequency is exactly n 19 khz (dcs locked to n pilot tone). the detection of the pilot and the stereo indication is done in the dsp program. 8.4.3 t he automatic lock system the vco of the dcs block will be at 19 khz 2 hz exact based in the event of no-pilot fm_mpx reception or in the event of only rds reception. in the event of stereo reception the phase error is zero for a pilot tone with a frequency of exactly 19 khz.
2001 mar 05 21 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 8.5 dcs clock in radio mode the stereo decoder, the adc3 and rds demodulator, the adc1 or adc2 and the level decimation filters have to run synchronously to the 19 khz pilot. therefore a clock signal with a controlled frequency of a multiple of 19 khz (9.728 mhz = 512 19 khz) is needed. in the saa7706h the patented method of non-equidistant digitally controlled sampling dcs clock has been implemented. by a special dividing mechanism a frequency of 9.728 mhz from the pll2 clock frequency of >40 mhz is generated. the dividing can be changed by means of i 2 c-bus bits to cope with the different input frequencies of the dcs block. the dcs system is controlled by up or down information from the stereo decoder. in the event of mono transmissions or 44.1 khz adc1 or adc2 usage the dcs clock is still controlled by the stereo decoder loop. the output keeps the dcs free running on a multiple frequency of 19 khz 2 hz if the correct clock setting is applied. in tape/cd of either 38 or 44.1 khz and am mode the dcs clock always has to be put in preset mode with a bit in the i 2 c-bus memory map definitions. 8.6 the interference absorption circuit (iac) 8.6.1 g eneral description the iac detects and suppresses ignition interference. this hardware iac is a modified, digitized and extended version of the analog circuit which is in use for many years already. the iac consists of an mpx mute function switched by mute pulses from ignition interference pulse detectors. the input signal of a second iac detection circuit is the fm level signal (the output of the level-adc). this detector performs optimally in lower antenna voltage circumstances. it is therefore complementary to the first detector. the input signal of a first iac detection circuit is the output signal of one of the down-sample paths coming from adc1 or adc2. this interference detector analyses the high-frequency contents of the mpx signal. the discrimination between interference pulses and other signals is performed by a special philips patented fuzzy logic such as algorithm and is based on probability calculations. this detector performs optimally in higher antenna voltage circumstances. on detection of ignition interference, this logic will send appropriate pulses to the mpx mute switch. the characteristics of both iac detectors can be adapted to the properties of different fm front-ends by means of the predefined coefficients in the iac control registers. the values can be changed via the i 2 c-bus. both iac detectors can be switched on or off independently of each other. both iac detectors can mute the mpx signal independently of each other. a third iac function is the dynamic iac circuit. this block is intended to switch off the iac completely the moment the mpx signal has a too high frequency deviation which in the event of small if filters can result in am modulation. this am modulation could be interpreted by the iac circuitry as interference caused by the cars engine. 8.7 the filter stream dac (fsdac) the fsdac is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. a post-filter is not needed due to the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage signal capable of driving a line output. the output voltage of the fsdac scales proportionally with the power supply voltage. 8.7.1 i nterpolation filter the digital filter interpolates from 1 to 64f s by means of a cascade of a recursive filter and an fir filter. table 2 digital interpolation ?lter characteristics 8.7.2 n oise shaper the 5th-order noise shaper operates at 64f s . it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. the noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. item conditions value (db) pass band ripple 0 - 0.45f s 0.03 stop band >0.55f s - 50 dynamic range 0 - 0.45f s 116.5 gain dc - 3.5
2001 mar 05 22 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 8.7.3 f unction of pin pom with pin pom it is possible to switch off the reference current of the dac. the capacitor on pin pom determines the time after which this current has a soft switch-on. so at power-on the current audio signal outputs are always muted. the loading of the external capacitor is done in two stages via two different current sources. the loading starts at a current level that is lower than the current loading after the voltage on pin pom has past a particular level. this results in an almost db-linear behaviour. this must prevent plop effects during power on or off. 8.7.4 p ower - off plop suppression to avoid plops in a power amplifier, the supply voltage of the analog part of the dac and the rest of the chip can be fed from a separate power supply of 3.3 v. a capacitor connected to this power supply enables to provide power to the analog part at the moment the digital voltage is switching off fast. in this event the output voltage will decrease gradually allowing the power amplifier some extra time to switch off without audible plops. 8.7.5 p in vrefda for internal reference with two internal resistors half the supply voltage v dda2 is obtained and used as an internal reference. this reference voltage is used as dc voltage for the output operational amplifiers and as reference for the dac. in order to obtain the lowest noise and to have the best ripple rejection, a filter capacitor has to be added between this pin and ground, preferably close to the analog pin v ssa2 . 8.7.6 s upply of the filter stream dac the entire analog circuitry of the dacs and the operational amplifiers are supplied by 2 supply pins: v dda2 and v ssa2 . v dda2 must have sufficient decoupling to prevent total harmonic distortion degradation and to ensure a good power supply rejection ratio. the digital part of the dac is fully supplied from the chip core supply. 8.8 clock circuit and oscillator the chip has an on-chip crystal clock oscillator. the block diagram of this pierce oscillator is shown in fig.13. the active element needed to compensate for the loss resistance of the crystal is the block g m . this block is placed between the external pins osc_in and osc_out. the gain of the oscillator is internally controlled by the agc block. a sine wave with a peak-to-peak voltage close to the oscillator power supply voltage is generated. the agc block prevents clipping of the sine wave and therefore the higher harmonics are as low as possible. at the same time the voltage of the sine wave is as high as possible which reduces the jitter going from sine wave to the clock signal. handbook, full pagewidth mgt469 agc g m r bias c2 c1 clock to circuit on-chip off-chip osc_in osc_out 63 64 v dd(osc) 0.5v dd(osc) v ss(osc) 65 62 fig.13 block diagram oscillator circuit.
2001 mar 05 23 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h handbook, full pagewidth mgt470 agc g m r bias c2 c1 c3 clock to circuit on-chip off-chip osc_in slave input 3.3 v(p-p) osc_out 63 64 v dd(osc) 0.5v dd(osc) v ss(osc) 65 62 fig.14 block diagram of the oscillator in slave mode. 8.8.1 s upply of the crystal oscillator the power supply connections of the oscillator are separated from the other supply lines. this is done to minimize the feedback from the ground bounce of the chip to the oscillator circuit. pin v ss(osc) is used as ground supply and pin v dd(osc) as positive supply. a series resistor plus capacitance is required for proper operating on pin v dd(osc) , see figs 25 and 26. see also important remark in section 8.10. 8.9 the phase-locked loop circuit to generate the dsps and other clocks there are several reasons why a pll circuit is used to generate the clock for the dsps: the pll makes it possible to switch in the rare cases that tuning on a multiple of the dsp clock frequency occurs to a slightly higher frequency for the clock of the dsp. in this way an undisturbed reception with respect to the dsp clock frequency is possible. crystals for the crystal oscillator in the range of twice the required dsp clock frequency, so approximately 100 mhz, are always third overtone crystals and must also be manufactured on customer demand. this makes these crystals expensive. the pll1 enables the use of a crystal running in the fundamental mode and also a general available crystal can be chosen. for this circuit a 256 44.1 khz = 11.2896 mhz crystal is chosen. this type of crystal is widely used. although a multiple of the frequency of the used crystal of 11.2896 mhz falls within the fm reception band, this will not disturb the reception because the relatively low frequency crystal is driven in a controlled way and the sine wave of the crystal has in the fm reception band only very minor harmonics. 8.10 supply of the digital part (v ddd3v1 to v ddd3v4 ) the supply voltage on pins v ddd3v1 to v ddd3v4 must be for at least 10 ms earlier active than the supply voltage applied to pin v dd(osc) . 8.11 cl_gen, audio clock recovery block when an external i 2 s-bus or spdif source is connected, the fsdac circuitry needs an 256f s related clock. this clock is recovered from either the incoming ws of the digital serial input or the ws derived from the spdif1/spdif2 input. there is also a possibility to provide the chip with an external clock, in that case it must be a 256f s clock with a fixed phase relation to the source.
2001 mar 05 24 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 8.12 external control pins 8.12.1 dsp1 for external control two input pins have been implemented. the status of these pins can be changed by applying a logic level. the status is saved in the dsp1 status register. the function of each pin depends on the dsp1 program. to control external devices two output pins are implemented. the status of these pins is controlled by the dsp program. function of these control pins can be found in a separate manual and is rom_code dependent. 8.12.2 dsp2 for external control four configurable i/o pins have been implemented. via the i 2 c-bus these four pins can be independently configured as input or output. the status of these pins can be changed by applying a logic level (input mode). the status is saved in the dsp2 status register. the function of each pin depends on the i 2 c-bus setting and dsp2 program. function of these control pins can be found in a separate manual and is rom_code dependent. 8.13 i 2 c-bus control (pins scl and sda) general information about the i 2 c-bus can be found in the i 2 c-bus and how to use it . this document can be ordered using the code 9398 393 40011. for the external control of the saa7706h device a fast i 2 c-bus is implemented. this is a 400 khz bus which is downward-compatible with the standard 100 khz bus. there are two different types of control instructions: instructions to control the dsp program, programming the coefficient ram and reading the values of parameters (level, multipath etc.) instructions controlling the data flow; such as source selection, iac control and clock speed. the detailed description of the i 2 c-bus and the description of the different bits in the memory map is given in chapter 9.
2001 mar 05 25 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 8.14 digital serial inputs/outputs and spdif inputs 8.14.1 g eneral description digital serial audio inputs / outputs for communication with external digital sources a digital serial bus is implemented. it is a serial 3-line bus, having one line for data, one line for clock and one line for the word select. for external digital sources the saa7706h acts as a slave, so the external source is master and supplies the clock. the digital serial input is capable of handling multiple input formats. the input is capable of handling philips i 2 s-bus and lsb-justified formats of 16, 18, 20 and 24 bits word sizes. the sampling frequency can be either 44.1 or 48 khz. see fig.15 for the general waveform formats of all possible formats. the number of bit clock (bck) pulses may vary in the application. when the applied word length is smaller than 24 bits (internal resolution of dsp2), the lsb bits will get internally a zero value; when the applied word length exceeds 24 bits then the lsbs are skipped. it should be noted that: two digital sources can not be used at the same time maximum number of bit clocks per word select (ws) is limited to 64 the word select (ws) must have a duty cycle of 50%. 8.14.2 g eneral description spdif inputs (spdif1 and spdif2) for communication with external digital sources also an spdif input can be used. the two spdif input pins can be connected via an analog multiplexer to the spdif receiver. it is a receiver without an analog pll that samples the incoming spdif with a high frequency. in this way the data is recovered synchronously on the applied system clock. from the spdif signal a three wire serial bus (e.g. i 2 s-bus) is made, consisting of a word select, data and bit clock line. the sample frequency f s depends solely on the spdif signal input accuracy and both 44.1 and 48 khz are supported. this chip does not handle the user data bits, channel status bits and validity bits of the spdif stream, but only the audio is given at its outputs. some rom_codes do take care of the pre-emphasis bit of the spdif stream. the bits in the audio space are always decoded regardless of any status bits e.g. copy protected, professional mode or data mode. the dac is not muted in the event of a non-linear pcm audio, however the bit is observable via the i 2 c-bus. a few other channel status bits are available. there are 5 control signals available from the spdif input stage. these are connected to flags of dsp2. for more details see separate manual. these 5 control signals are: signals to indicate the sample frequency of the spdif signal: 44.1 and 48 khz (32 khz is not supported) a lock signal indicating if the spdif input is in lock the pre-emphasis bit of the spdif audio stream the pcm_audio/non-pcm_audio bit indicating if an audio or data stream is detected. the fsdac output will not be muted in the event of a non-audio pcm stream. this status bit can be read via the i 2 c-bus, the microcontroller can decide to mute the dac (via pin pom). the design fulfils the digital audio interface specification iec 60958-1 ed2, part 1, general part iec 60958-3 ed2, part 3, consumer applications . it should be noted that: the spdif input may only be used in the consumer mode specified in the digital audio interface specification only one of the two spdif sources can be used (selected) at the same time the fsdac will not (automatically) be muted in the event of a non-audio stream two digital sources can not be used at the same time supported sample frequencies are 44.1 and 48 khz.
2001 mar 05 26 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 8.14.3 d igital data stream formats handbook, full pagewidth mgr751 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24 bits ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20 bits ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 left lsb-justified format 18 bits ws bck data right 15 18 17 2 1 msb b2 b3 b4 b17 lsb 16 15 18 17 2 1 b17 lsb 16 msb b2 left lsb-justified format 16 bits ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb msb msb b2 2 1 > = 8 12 3 left input format i 2 s-bus ws bck data right 3 > = 8 msb b2 fig.15 all serial data input/output formats.
2001 mar 05 27 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 8.15 rds demodulator (pins rds_clock and rds_data) the rds demodulator recovers the additional inaudible rds information which is transmitted by fm radio broadcasting. the (buffered) data is provided as output for further processing by a suitable decoder. the operational functions of the decoder are in accordance with the ebu specification en 50067 . the rds demodulator has three different functions: clock and data recovery from the mpx signal buffering of 16 bits, if selected interfacing with the microcontroller. 8.15.1 c lock and data recovery the rds-chain has a separate input. this enables rds updates during tape play and also the use of a second receiver for monitoring the rds information of signals from an other transmitter (double tuner concept). it can as such be done without interruption of the audio program. the mpx signal from the main tuner of the car radio can be connected to this rds input via the built-in source selector. the input selection is controlled by an i 2 c-bus bit. the rds chain contains a sigma-delta adc (adc3), followed by two decimation filters. the first filter passes the multiplex band including the signals around 57 khz and reduces the sigma-delta noise. the second filter reduces the rds bandwidth around 57 khz. the overall filter curve is shown in fig.16 and a more detailed curve of the rds 57 khz band in fig.17. handbook, full pagewidth 152 0 - 100 0 38 114 mgt471 76 133 19 95 57 - 80 - 60 - 40 - 20 f (khz) a (db) fig.16 overall frequency response curve decimation filters.
2001 mar 05 28 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h handbook, full pagewidth 10 - 70 50 54 62 mgt472 58 64 52 60 56 - 30 - 20 - 10 - 60 - 50 - 40 0 f (khz) a (db) fig.17 detailed frequency response curve rds channel. the quadrature mixer converts the rds band to the frequency spectrum around 0 hz and contains the appropriate q/i signal filters. the final decoder with cordic recovers the clock and data signals. these signals are output on pins rds_clock and rds_data. in the event of fm-stereo reception the clock of the total chip is locked to the stereo pilot (19 khz multiple). in the event of fm-mono the dcs loop keeps the dcs clock around the same 19 khz multiple. in all other cases like am reception or tape, the dcs circuit has to be set in a preset position by means of an i 2 c-bus bit. under these conditions the rds system is always clocked by the dcs clock in a 38 khz (4 9.5 khz) based sequence. 8.15.2 t iming of clock and data signals the timing of the clock and data output is derived from the incoming data signal. under stable conditions the data will remain valid for 400 m s after the clock transition. the timing of the data change is 100 m s before a positive clock change. this timing is suited for positive as well as negative triggered interrupts on a microcontroller. the rds timing is shown in fig.18. during poor reception it is possible that faults in phase occur, then the duty cycle of the clock and data signals will vary from minimum 0.5 times to a maximum of 1.5 times the standard clock periods. normally, faults in phase do not occur on a cyclic basis.
2001 mar 05 29 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h handbook, full pagewidth mgu270 rds_data rds_clock t su t hc t lc t h t cy fig.18 rds timing in the direct output mode. 8.15.3 b uffering of rds data the repetition of the rds data is around the 1187 hz. this results in an interrupt on the microcontroller for every 842 m s. in a second mode, the rds interface has a double 16-bit buffer. 8.15.4 b uffer interface the rds interface buffers 16 data bits. every time 16 bits are received, the data line is pulled down and the buffer is overwritten. the microcontroller has to monitor the data line in at most every 13.5 ms. this mode can be selected via an i 2 c-bus. in fig.19 the interface signals from the rds decoder and the microcontroller in buffer mode are shown. when the buffer is filled with 16 bits the data line is pulled down. the data line will remain low until reading of the buffer is started by pulling down the clock line. the first bit is clocked out. after 16 clock pulses the reading of the buffer is ready and the data line is set high until the buffer is filled again. the microcontroller stops communication by pulling the line high. the data is written out just after the clock high-to-low transition. the data is valid when the clock is high. when a new 16-bit buffer is filled before the other buffer is read, that buffer will be overwritten and the old data is lost.
2001 mar 05 30 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h handbook, full pagewidth mgu271 d0 d1 d2 d13 d14 d15 rds_data rds_clock t w t hc t lc block ready start reading data t cy fig.19 interface signals rds decoder and microcontroller (buffer mode). 8.16 dsp reset pin dsp_reset is active low and requires an external pull-up resistor. between this pin and the v ssd ground a capacitor should be connected to allow a proper switch-on of the supply voltage. the capacitor value is such that the chip is in reset as long as the power supply is not stabilized. a more or less fixed relationship between the dsp_reset (pin) and the pom (pin) time constant is mandatory. the voltage on pin pom determines the current flowing in the dacs. at 0 v on pin pom the dac currents are zero and so are the dac output voltages. at the v dda2 voltage the dac currents are at their nominal (maximal) value. long before the dac outputs get to their nominal output voltages, the dsp must be in working mode to reset the output register: therefore the dsp time constant must be shorter than the pom time constant. for recommended capacitors see figs 25 and 26. the reset has the following function: all i 2 c-bus bits are set to their default value the dsp status registers (dsp1 and dsp2) are reset the program counter of both dsps are set to address 0000h the two output flags of dsp1 (dsp1_out1 and dsp1_out2) are reset to logic 0. all the configurable flags of dsp2 are reset to logic 0, however the four flags available at the output of the chip are default configured as input flags (dsp2_inout1, dsp2_inout2, dsp2_inout3 and dsp2_inout4). when the level on pin dsp_reset is at high, the dsp program (dsp1 and dsp2) starts to run. 8.17 test mode connections (pins tscan, rtcb and shtcb) pins tscan, rtcb and shtcb are used to put the chip in test mode and to test the internal connections. each pin has an internal pull-down resistor to ground. in the application these pins can be left open or connected to ground.
2001 mar 05 31 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 9i 2 c-bus format for more general information on the i 2 c-bus protocol, see the philips i 2 c-bus specification. 9.1 addressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always done with the first byte transmitted after the start procedure. 9.2 slave address (pin a0) the saa7706h acts as slave receiver or a slave transmitter. therefore the clock signal scl is only an input signal. the data signal sda is a bidirectional line. the saa7706h slave address is shown in table 3. table 3 slave address the sub-address bit a0 corresponds to the hardware address pin a0 which allows the device to have 2 different addresses. the a0 input is also used in test mode as a serial input of the test control block. 9.3 write cycles the i 2 c-bus configuration for a write cycle is shown in fig.20. the write cycle is used to write the bytes to both dsp1 and dsp2 for manipulating the data and coefficients. depending on which dsp is accessed the data protocol exists out of 2, 3 or 4 bytes. more details can be found in the i 2 c-bus memory map (see table 5). the data length is 2, 3 or 4 bytes depending on the accessed memory. if the y-memory of dsp1 is addressed the data length is 2 bytes, in the event of the x-memory of dsp1 or x/y-memory of dsp2 the length is 3 bytes. the slave receiver detects the address and adjusts the number of bytes accordingly. the data length of 4 bytes is not used in the saa7706h. 9.4 read cycles the i 2 c-bus configuration for a read cycle is shown in fig.21. the read cycle is used to read the data values from xram or yram of both dsps. the master starts with a start condition s, the saa7706h address 0011100 and a logic 0 (write) for the r/ w bit. this is followed by an acknowledge of the saa7706h. then the master writes the high memory address and low memory address where the reading of the memory content of the saa7706h must start. the saa7706h acknowledges these addresses both. then the master generates a repeated start (sr) and again the saa7706h address 0011100 but this time followed by a logic 1 (read) of the r/ w bit. from this moment on the saa7706h will send the memory content in groups of 2 (y-memory dsp1) or 3 (x-memory dsp1, x/y-memory dsp2 or registers) bytes to the i 2 c-bus each time acknowledged by the master. the master stops this cycle by generating a negative acknowledge, then the saa7706h frees the i 2 c-bus and the master can generate a stop condition. the data is transferred from the dsp register to the i 2 c-bus register at execution of the mpi instruction in the dsp2 program. therefore at least once every dsp routine an mpi instruction should be added. the data length of 4 bytes is not used in the saa7706h. 9.5 saa7706h hardware registers the write cycle can be used to write the bytes to the hardware registers to control the dcs block, the pll for the dsp clock generation, the iac settings, the ad volume control settings, the analog input selection, the format of the i 2 s-bus and some other settings. it is also possible to read these locations for chip status information. more detail can be found in the i 2 c-bus memory map, tables 4 and 5. 9.5.1 saa7706h dsp s registers the hardware registers have two different address blocks. one block exists out of hardware register locations which control both dsps and some major settings such as the pll division. these locations have a maximum of 16 bits, which means 2 bytes need to be sent to or read from. for the saa7706h one register is located at the dsps and general control register (0fffh). the second block has an address space of 16 addresses and are all x-memory mapped on dsp2. while this space is 24 bits wide 3 bytes should be sent to or read from. these addresses are dsp2 mapped which means an mpi instruction is needed for accessing those locations and there is no verifying mechanism if all addresses are really mapped to physical registers. therefore, all those locations will be acknowledged even if the data is not valid. for the saa7706h several registers are located in this section. a few registers are predefined for dsp2 purposes (see table 5). msb lsb 0 01110a0r/ w
2001 mar 05 32 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 0111000 a c k a c k a c k a c k a c k address s 0 addr h addr l data h data m r/w mgd568 auto increment if repeated n-groups of 3 (2) bytes p a c k data l fig.20 master transmitter writes to the saa7706h registers. s = start condition p = stop condition ack = acknowledge from saa7706h addr h and addr l = address dsp register data 1, data 2, data3 and data 4 = 2, 3 or 4 bytes data word. 0111000 a c k a c k a c k a c k a c k address s 0 011 1 100 s 0 addr h addr l data h r/w mga808 - 1 auto increment if repeated n-groups of 3 (2) bytes p a c k a c k data m data l r/w fig.21 master transmitter reads from the saa7706h registers. s = start condition sr = repeated start condition p = stop condition ack = acknowledge from saa7706h (sda low) r = repeat n-times the 2, 3 or 4 bytes data group na = negative acknowledge master (sda high) addr h and addr l = address dsp register data 1, data 2, data 3 and data 4 = 2, 3 or 4 bytes data word.
2001 mar 05 33 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 9.6 i 2 c-bus memory map speci?cation the i 2 c-bus memory map contains all defined i 2 c-bus bits. the map is split up in two different sections, the hardware memory registers and the ram definitions. in table 5 the preliminary memory map is depicted. the hardware registers are memory map on the xram of dsp2. table 5 shows the detailed memory map of those locations. all locations are acknowledged by the saa7706h even if the user tries to write to a reserved space. the data in these sections will be lost. reading from this locations will result in undefined data words. table 4 i 2 c-bus memory map table 5 i 2 c-bus memory map overview of hardware registers address function size 2000h to 21ffh yram (dsp2) 512 12 bits 1ff0h to 1fffh hardware registers 16 24 bits 1000h to 127fh xram (dsp2) 640 24 bits 0fffh dsp control 1 16 bits 0800h to 097fh yram (dsp1) 384 12 bits 0000h to 017fh xram (dsp1) 384 18 bits description register hardware registers program counter register dsp2 1fffh status register dsp2 1ffeh i/o con?guration register dsp2 1ffdh phone, navigation and audio register 1ffch fm and rds sensitivity register 1ffbh clock coef?cient register 1ffah clock settings register 1ff9h iac settings register 1ff8h selector register 1ff7h cl_gen register 4 1ff6h cl_gen register 3 1ff5h cl_gen register 2 1ff4h cl_gen register 1 1ff3h evaluation register 1ff0h dsp control dsps and general control register 0fffh
2001 mar 05 34 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 10 limiting values in accordance with the absolute maximum ratings system (iec 60134). 11 thermal characteristics 12 characteristics v dd = 3 to 3.6 v; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage - 0.5 +3.6 v v n input voltage on any pin - 0.5 +5.5 v i ik dc input clamping diode current v i < - 0.5 v or v i >v dd + 0.5 v - 10 ma i ok dc output clamping diode current v o < - 0.5 v or v o >v dd + 0.5 v - 20 ma i o(sink/source) dc output source or sink current - 0.5v 2001 mar 05 35 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h p tot total power dissipation dsp1 at 50 mhz, dsp2 at 62.9 mhz - 540 750 mw digital i/o; t amb = - 40 to +85 c; v dd = 3 to 3.6 v v ih high-level input voltage for all digital inputs and i/os 2.0 -- v v il low-level input voltage for all digital inputs and i/os -- 0.8 v v hys schmitt trigger hysteresis voltage 0.4 -- v v oh high-level output voltage standard output; i o = - 4ma v dd - 0.4 -- v 5 ns slew rate output; i o = - 4ma v dd - 0.4 -- v 10 ns slew rate output; i o = - 2ma v dd - 0.4 -- v 20 ns slew rate output; i o = - 1ma v dd - 0.4 -- v v ol low-level output voltage standard output; i o =4ma -- 0.4 v 5 ns slew rate output; i o = 4ma -- 0.4 v 10 ns slew rate output; i o =2ma -- 0.4 v 20 ns slew rate output; i o =1ma -- 0.4 v i 2 c-bus output; i o =4ma -- 0.4 v i lo output leakage current 3-state outputs v o = 0 v or v dd -- 5 m a r pd internal pull-down resistor to v ss 24 50 140 k w r pu internal pull-up resistor to v dd 30 50 100 k w c i input capacitance -- 3.5 pf t i(r) ,t i(f) input rise and fall times v dd = 3.6 v - 6 200 ns t o(t) output transition time standard output; c l =30pf - 3.5 - ns 5 ns slew rate output; c l =30pf - 5 - ns 10 ns slew rate output; c l =30pf - 10 - ns 20 ns slew rate output; c l =30pf - 20 - ns i 2 c-bus output; c b = 400 pf 60 - 300 ns symbol parameter conditions min. typ. max. unit
2001 mar 05 36 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h analog inputs; t amb =25 c; v dda1 = 3.3 v dc characteristics common mode reference voltage adc1, adc2 and level-adc with reference to v ssa1 0.47 0.50 0.53 z o(vrefad) output impedance at pin vrefad - 10 -w v vdacp positive reference voltage adc1, 2, 3 and level-adc 3 3.3 3.6 v i vdacp positive reference current adc1, 2, 3 and level-adc -- 200 -m a v vdacn1 , v vdacn2 negative reference voltage adc1, 2, 3 and level-adc - 0.3 0 +0.3 v i vdacn1 , i vdacn2 negative reference current adc1, 2 and 3 - 200 -m a v io(adc) input offset voltage adc1, 2 and 3 - 140 - mv ac characteristics v i(con)(max)(rms) maximum conversion input level (rms value) cd, tape, am and aux input signals thd <1% 0.6 0.66 - v fm_mpx input signal thd <1%; volfm = 00h 0.33 0.368 - v r i input impedance cd, tape, am and aux input signals 1 -- m w fm_mpx input signal 48 60 72 k w thd total harmonic distortion cd, tape, am and aux input signals input signal 0.55 v (rms) at 1 khz; bandwidth = 20 khz; f s = 44.1 khz -- 85 - 75 db fm_mpx input signal input signal 368 mv (rms) at 1 khz; bandwidth = 19 khz; volfm = 00h -- 70 - 65 db - 0.03 0.056 % symbol parameter conditions min. typ. max. unit v vrefad v vdda1 ----------------------
2001 mar 05 37 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h s/n signal-to-noise ratio cd, tape, am and aux input signals input signal at 1 khz; bandwidth = 20 khz; 0 db reference = 0.55 v (rms); f s = 44.1 khz 85 90 - db fm_mpx input signal mono input signal at 1 khz; bandwidth = 19 khz; 0 db reference = 0.368 v (rms); volfm = 00h 80 83 - db fm_mpx input signal stereo input signal at 1 khz; bandwidth = 40 khz; 0 db reference = 0.368 v (rms); volfm = 00h 75 81 - db a 19 carrier and harmonic suppression at the output pilot signal frequency = 19 khz - 81 - db unmodulated - 98 - db a 38 carrier and harmonic suppression at the output subcarrier frequency = 38 khz - 83 - db unmodulated - 91 - db a 57 carrier and harmonic suppression for 19 khz, including notch subcarrier frequency = 57 khz - 83 - db unmodulated - 96 - db a 76 carrier and harmonic suppression for 19 khz, including notch subcarrier frequency = 76 khz - 84 - db unmodulated - 94 - db im a 10 intermodulation f mod = 10 khz; f spur = 1 khz 77 -- db im a 13 intermodulation f mod = 13 khz; f spur = 1 khz 76 -- db a 57(vf) traf?c radio suppression f = 57 khz - 110 - db a 67(sca) subsidiary communication authority (sca) suppression f = 67 khz - 110 - db a 114 adjacent channel suppression f = 114 khz - 110 - db a 190 adjacent channel suppression f = 190 khz - 110 - db v th(pilot)(rms) pilot threshold voltage (rms value) at pin dsp1_out1 stereo on; volfm = 07h - 35.5 - mv stereo off; volfm = 07h - 35.4 - mv hys hysteresis of v th(pilot)(rms) - 0 - db a cs1 channel separation fm-stereo input f i = 1 khz 40 45 - db f i = 10 khz 25 30 - db a cs2 channel separation cd, tape, am and aux input signals 60 70 - db symbol parameter conditions min. typ. max. unit
2001 mar 05 38 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h f res audio frequency response cd, tape, am and aux input signals f s = 44.1 khz; at - 3db 20 -- khz fm_mpx input signal at - 3 db via dsp at dac output 17 -- khz d g l-r overall left/right gain unbalance (tape, cd, aux and am input signals) -- 0.5 db a ct crosstalk between inputs f i = 1 khz 65 -- db f i = 15 khz 50 -- db psrr mpx/rds power supply ripple rejection mpx and rds adcs output via i 2 s-bus; adc input short-circuited; f ripple = 1 khz; v ripple = 100 mv (peak); c vrefad =22 m f; c vdacp =10 m f 35 45 - db psrr lad power supply ripple rejection level-adc output via dac; adc input short-circuited; f ripple = 1 khz; v ripple = 100 mv (peak); c vrefad =22 m f 29 39 - db cmrr cd common-mode rejection ratio for cd input mode r cd_(l)_gnd =1m w ; resistance of cd player ground cable < 1 k w; f i = 1 khz 60 -- db ac characteristics phone and nav inputs; t amb =25 c; v dda1 = 3.3 v thd total harmonic distortion of phone and nav input signals at maximum input voltage v i = 0.75 v (rms); f i = 1 khz; volmix = 30h; measured at flv and frv outputs 40 -- db cmrr common mode rejection ratio of phone and nav input signals v i = 0.75 v(rms); f i = 1 khz; volmix = 30h 25 50 - db r i input impedance of phone, nav/am_l and am_r input signals 90 120 150 k w v i(max)(rms) maximum input level of phone and nav input signals (rms value) f i = 1 khz; volmix = 30h 0.75 1 - v ac characteristics fm_rds input; t amb =25 c; v dda1 = 3.3 v v i(con)(max)(rms) maximum conversion level of fm_rds input (rms value) thd < 1%; volrds = 00h 0.33 0.368 - v r i(fm_rds) input resistance fm_rds input 40 60 72 k w thd fm_rds total harmonic distortion rds adc f c =57khz - 60 - 67 - db symbol parameter conditions min. typ. max. unit
2001 mar 05 39 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h s/n fmrds signal-to-noise ratio rds adc 6 khz bandwidth; f c = 57 khz; 0 db reference = 0.55 v (rms); volrds = 00h 54 -- db a pilot pilot attenuation rds 50 -- db a nearby selectivity rds neighbouring channel at 200 khz distance 61 -- db a n(adc) rds adc noise attenuation 70 -- db v ripple(rds) ripple voltage rds pass band 2.4 khz bandwidth -- 0.5 db a mux(rds) multiplex attenuation rds mono 70 -- db stereo 40 -- db d f osc allowable frequency deviation of the 57 khz rds maximum crystal resonance frequency deviation of 100 ppm -- 6hz ac characteristics spdif1 and spdif2 inputs; t amb =25 c; v dda2 = 3.3 v v i(p-p) ac input level (peak-to-peak level) 0.2 0.5 3.3 v r i input impedance at 1 khz - 6 - k w v hys hysteresis of input voltage - 40 - mv ac characteristics analog level input; t amb =25 c; v dda1 = 3.3 v s/n lad signal-to-noise ratio of level-adc 0 to 29 khz bandwidth; maximum input level; unweighted 48 54 - db r i input resistance 1.0 - 2.2 m w v i(fs)(lad) full-scale level-adc input voltage 0 - v dda1 v v io dc offset voltage -- 120 mv a decimation ?lter attenuation 20 -- f co(pb) pass band cut-off frequency at - 3 db and dcs clock = 9.728 mhz - 29 - khz f sr sample rate frequency after decimation dcs clock = 9.728 mhz - 38 - khz analog dac outputs on pins flv, frv, rlv and rrv; t amb =25 c; v dda2 = 3.3 v; f s = 44.1 khz; r l =5k w ; f i = 1 khz dc characteristics r o(ref) reference output resistance pin vrefda - 14 - k w r o dac output resistance pins flv, frv, rlv and rrv - 0.13 3.0 w i o(max) maximum output current (thd + n)/s < 0.1%; r l =5k w - 0.22 - ma r l load resistance 3 -- k w symbol parameter conditions min. typ. max. unit db decade -------------------
2001 mar 05 40 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 13 rds and i 2 s-bus timing t amb =25 c; v ddd = 3.3 v; unless otherwise speci?ed. c l load capacitance -- 200 pf ac characteristics v o(rms) output voltage (rms value) - 1000 - mv d v o unbalance between channels - 0.1 - db (thd + n)/s total harmonic distortion-plus-noise to signal ratio (measured with system one) at 0 db -- 90 - 85 db at - 60 db; a-weighted -- 37 - db s/n signal-to-noise ratio (measured with system one) code = 0; a-weighted - 105 - db a cs channel separation - 80 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple(p-p) =1% - 50 - db oscillator; t amb =25 c; v dd(osc) = 3.3 v f xtal crystal frequency - 11.2896 - mhz v xtal voltage across the crystal crystal series resistance r s < 100 w ; crystal shunt capacitance c p < 7 pf; crystal load capacitance c l = 12 pf; c 1 =c 2 =22pf (see fig.13) 1.6 2.6 3.6 v i dd(osc) supply current crystal oscillator at start-up 1.7 3.4 6.4 ma at oscillation - 0.32 - ma symbol parameter conditions min. typ. max. unit rds timing (see figs 18 and 19) f rdsclk nominal rds clock frequency - 1187.5 - hz t su clock set-up time direct output mode 100 --m s t cy cycle time direct output mode - 842 -m s buffer mode 2 --m s t hc clock high time direct output mode 220 - 640 m s buffer mode 1 --m s t lc clock low time direct output mode 220 - 640 m s buffer mode 1 --m s t h data hold time 100 --m s t w wait time buffer mode 1 --m s symbol parameter conditions min. typ. max. unit
2001 mar 05 41 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h i 2 s-bus timing (see fig.23) t r rise time t cy = 325 ns -- 0.15t cy ns t f fall time t cy = 325 ns -- 0.15t cy ns t cy bit clock cycle time 325 -- ns t bck(h) bit clock time high t cy = 325 ns 0.35t cy -- ns t bck(l) bit clock time low t cy = 325 ns 0.35t cy -- ns t su(d) data set-up time t cy = 325 ns 0.2t cy -- ns t h(d) data hold time t cy = 325 ns 0.2t cy -- ns t d(d) data delay time t cy = 325 ns -- 0.15t cy ns t su(ws) word select set-up time t cy = 325 ns 0.2t cy -- ns t h(ws) word select hold time t cy = 325 ns 0.2t cy -- ns symbol parameter conditions min. typ. max. unit handbook, full pagewidth ws bck data in right lsb msb left t su(ws) t h(ws) t su(d) t h(d) t bck(h) t d(d) t bck(l) t cy t r t f mgm129 data out lsb msb fig.23 input timing digital audio data inputs.
2001 mar 05 42 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 14 i 2 c-bus timing t amb =25 c; v ddd = 3.3 v; unless otherwise speci?ed. symbol parameter conditions standard mode i 2 c-bus fast mode i 2 c-bus unit min. max. min. max. f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 - 1.3 -m s t hd;sta hold time (repeated) start condition. after this period, the ?rst clock pulse is generated 4.0 - 0.6 -m s t low low period of the scl clock 4.7 - 1.3 -m s t high high period of the scl clock 4.0 - 0.6 -m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 -m s t hd;dat data hold time 0 - 0 0.9 m s t su;dat data set-up time 250 - 100 - ns t r rise time of both sda and scl signals c b in pf - 1000 20 + 0.1c b 300 ns t f fall time of both sda and scl signals c b in pf - 300 20 + 0.1c b 300 ns t su;sto set-up time for stop condition 4.0 - 0.6 -m s c b capacitive load for each bus line - 400 - 400 pf t sp pulse width of spikes to be suppressed by input ?lter -- 050ns
2001 mar 05 43 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h handbook, full pagewidth msc610 s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta fig.24 definition of timing on the i 2 c-bus. 15 software description the use and description of the software features of the saa7706h will be described in the separate application manual. 16 application diagram the application diagram shown in figs 25 and 26 must be considered as one of the examples of a (limited) application of the chip e.g. in this case the i 2 s-bus inputs of the cd-input are not used. for the real application set-up the information of the application report is necessary.
2001 mar 05 44 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h handbook, full pagewidth mgt473 fm_rds 79 level adc rds demodulator xtal oscillator mono adc3 stereo adc2 stereo adc1 analog source selector sel_fr rds data rds clock 61 fm_mpx 80 tape_r 68 tape_l 69 cd_r_gnd 14 stereo cmrr inputs vrefad 78 vdacn1 2 vdacp 1 cd_r 70 cd_(l)_gnd 77 cd_l 72 nav_gnd 4 mono cmrr inputs level 3 rtcb 43 shtcb 44 tscan 45 v dda1 74 vdacn2 76 v ssa1 75 v ddd3v5 v ddd v dda 46 v ddd3v6 36 v ddd3v7 22 v ssd3v1 49 v ssd3v2 50 v ssd3v3 53 v ssd3v4 54 v ssd3v5 47 v ssd3v6 37 v ssd3v7 23 22 nf c45 c43 100 m f c3 220 pf c5 220 nf c1 470 nf l2 r35 10 w r34 10 w r1 15 k w v ss(osc) 62 v dd(osc) 65 tp1 21 osc_out 64 osc_in 63 rds_clock 59 rds_data 60 phone_gnd 73 phone phone level 71 c2 470 nf r2 15 k w r3 100 k w c4 220 pf r4 27 k w r5 100 k w c9 100 pf c6 1 m f r6 8.2 k w cd-l cd-gnd c7 47 m f r8 10 k w c10 100 pf cd-r c8 1 m f r7 8.2 k w r9 10 k w aux_r 8 aux_l 7 am_r/am 66 am_l/nav 67 saa7706h a b c d e 22 m f c12 47 nf c11 100 pf c14 220 nf c13 100 k w 1 m w r16 100 k w r11 100 pf c16 220 nf c15 100 k w r18 100 k w r13 r10 100 pf c18 220 nf c17 100 k w r38 56 k w r15 100 pf c20 220 nf c19 100 k w r39 56 k w r17 27 pf c21 22 k w r19 1 m f c22 am-l/nav am-r/am tape-l tape-r 100 pf c47 220 nf 82 k w r37 aux-l 100 pf c48 220 nf 82 k w r39 aux-r fm c48 47 m f c24 18 pf c23 100 nf c25 18 pf x1 11.2896 mhz 10 w r36 v dda l1 fig.25 application diagram (continued in fig.26).
2001 mar 05 45 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h handbook, full pagewidth mgt474 digital source selectors digital i/o digital source selector spdif2 spdif2 spdif1 i 2 s-bus spdif sda scl a i 2 c-bus 25 24 cd_data 28 signal level dsp1 dsp2 quad fsdac 16 flv 13 frv 9 rlv 6 rrv front-left front-right rear-left rear-right 5 pom t1 + 5 v microcontroller 10 v ssa2 11 v dda2 20 loopo b cd_ws 27 cd_clk 29 a0 56 dsp_reset 42 v ddd v ddd v ddd3v1 48 v ddd3v2 51 v ddd3v3 52 v ddd3v4 55 41 40 39 dsp-flags 38 19 18 15 17 sysfs 26 sda 58 scl 57 microcontroller signal quality phone volume r37 4.7 k w r24 910 w r25 4.7 k w iac saa7706h stereo decoder + 12 vrefda 34 iis_out1 35 iis_out2 30 iis_clk 33 iis_ws 31 iis_in1 32 iis_in2 a b c d e + 5 v + 5 v r23 10 k w r22 10 k w c32 100 nf c26 100 pf c31 22 m f c30 1 m f c33 22 m f 10 m f c34 10 m f c36 10 m f c38 10 m f c40 c42 4.7 m f c35 10 nf r20 75 w 100 w r27 10 k w r26 100 nf c27 spdif1 c28 100 pf r21 75 w 100 nf c29 dsp1_out2 dsp1_out1 dsp1_in2 dsp1_in1 dsp2_inout4 dsp2_inout3 dsp2_inout2 dsp2_inout1 + c37 10 nf 100 w r29 10 k w r28 c39 10 nf 100 w r31 10 k w r30 c41 10 nf 100 w r33 10 k w r32 fig.26 application diagram (continued from fig.25).
2001 mar 05 46 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 17 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.45 0.30 0.25 0.14 14.1 13.9 0.8 1.95 18.2 17.6 1.2 0.8 7 0 o o 0.2 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot318-2 mo-112 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.0 0.6 d b p e q e a 1 a l p detail x l (a ) 3 b 24 c b p e h a 2 d z d a z e e v m a 1 80 65 64 41 40 25 pin 1 index x y d h v m b w m w m 97-08-01 99-12-27 0 5 10 mm scale qfp80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot318-2 a max. 3.2
2001 mar 05 47 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 18 soldering 18.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 18.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 18.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2001 mar 05 48 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 18.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2001 mar 05 49 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h 19 data sheet status note 1. please consult the most recently issued data sheet before initiating or completing a design. data sheet status product status definitions (1) objective speci?cation development this data sheet contains the design target or goal speci?cations for product development. speci?cation may change in any manner without notice. preliminary speci?cation quali?cation this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation production this data sheet contains ?nal speci?cations. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. 20 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 22 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2001 mar 05 50 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h notes
2001 mar 05 51 philips semiconductors product speci?cation car radio digital signal processor (dsp) saa7706h notes
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20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 5f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2451, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna trad road km. 3, bagna, bangkok 10260, tel. +66 2 361 7910, fax. +66 2 398 3447 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753503/25/01/pp 52 date of release: 2001 mar 05 document order number: 9397 750 07096

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